Title :
Modeling techniques to support system level simulation and a top-down development methodology
Author :
Gravenstein, Martin
Author_Institution :
Ford Electron. Div., Ford Microelectron. Inc., Colorado Springs, CO, USA
Abstract :
This paper describes several effective Verilog coding techniques which, by increasing simulation performance, enable a seamless migration of a large scale electronic system through a wide range of abstraction for both the system description and the simulated verification. These coding techniques support the maintenance of design integrity during either forward or backward abstraction migration. This is accomplished by supporting mixed levels of detail for different system functions, and for the same system function at different time periods, during simulation
Keywords :
circuit analysis computing; specification languages; Verilog coding techniques; abstraction; design integrity; modeling techniques; simulated verification; system description; system level simulation; top-down development methodology; Computational modeling; Design automation; Discrete event simulation; Electronic design automation and methodology; Engines; Equations; Hardware design languages; Large-scale systems; Performance analysis; Time division multiplexing;
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
DOI :
10.1109/IVC.1994.323749
