Title :
Structured board level simulation using Verilog
Author :
Wanzenried, Roland
Abstract :
Board level simulation is an area of growing interest given the high levels of integration and complexity on boards today. The main motivation for performing a board level simulation is to improve design quality and shorten the design cycle through fewer circuit board turns. This paper presents a high level interface method used to control a board level simulation that has been implemented on an acquisition board design within Tektronix. The main strategic advantages to the interface method that was used include re-usability of the simulation modules, a simplified interface for firmware verification, and versatility in sub-section testing
Keywords :
application specific integrated circuits; firmware; logic CAD; specification languages; ASIC; Verilog; design cycle; design quality; firmware verification; high level interface method; structured board level simulation; versatility; Circuit simulation; Connectors; Hardware design languages; Microprocessors; Microprogramming; Printed circuits; Process control; Read only memory; Testing; Timing;
Conference_Titel :
Verilog HDL Conference, 1994., International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-5655-7
DOI :
10.1109/IVC.1994.323751
