Title :
A scheduling and partitioning scheme for low power circuit operating at multiple voltages
Author :
Wang, Ling ; Selvaraj, Henry
Author_Institution :
Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA
Abstract :
In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; low-power electronics; processor scheduling; resource allocation; voltage multipliers; CMOS VLSI; low power circuit; multiple voltage operation; partitioning scheme; power dissipation minimization; resource constrained partitioning; resource constrained scheduling; scheduling scheme; time-constrained partitioning; time-constrained scheduling; Circuits; Hardware; High level synthesis; Power dissipation; Power engineering and energy; Power engineering computing; Processor scheduling; Signal synthesis; Very large scale integration; Voltage;
Conference_Titel :
Digital System Design, 2003. Proceedings. Euromicro Symposium on
Conference_Location :
Belek-Antalya, Turkey
Print_ISBN :
0-7695-2003-0
DOI :
10.1109/DSD.2003.1231915
