A system for floorplanning with hierarchical placement and wiring

Hierarchical physical design is essential for large VLSI chips. This paper describes a new efficient floorplanning system designed to work within a hierarchical design environment; it supports either `strict´ or `pseudo´-hierarchy, and multiple design styles. The authors have demonstrated that their mix of interactive and automatic floorplanning tools allows users to significantly improve the control of timing and wirability on VLSI designs