Title :
Applying testability to an ASIC architectural core
Author :
Couleur, Jody ; Cravatta, Sam
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
The device-level testing of an application-specific integrated circuit (ASIC) that is designed using VLSI cores and LSI peripheral cells is discussed. The Intel ASIC UCS51 microcontroller product family is described, and the UCS51 test methodology is compared to that of the Intel standard product 80C51. A solution that provides the ASIC customer with a flexible design environment without compromising device testing is accomplished by employing built-in test modes, which are designed into the microcontroller core and accessed through a minimal amount of device package pins
Keywords :
VLSI; application specific integrated circuits; integrated circuit testing; microcontrollers; ASIC architectural core; Intel ASIC UCS51 microcontroller product family; LSI peripheral cells; VLSI cores; built-in test modes; device package pins; device-level testing; flexible design environment; test methodology; testability; Application specific integrated circuits; Circuit testing; Large scale integration; Life testing; Logic testing; Packaging; Pins; Semiconductor device testing; Standards development; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123192