Energy characterization of a tiled architecture processor with on-chip networks

Author

Kim, Jason Sungtae ; Taylor, Michael Bedford ; Miller, Jason ; Wentzlaff, David

Author_Institution

Lab. for Comput. Sci., MIT, Cambridge, MA, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

424

Lastpage

427

Abstract

Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units,and over 250 unique processor pipeline, stages, all according to the needs of the computation and environment at hand.

Keywords

SRAM chips; low-power electronics; microprocessor chips; parallel architectures; pipeline processing; ASIC; Raw microprocessor; SRAM macros; distributed parallel architectures; fetch units; functional unit clusters; on-chip networks; power management facilities; processor pipeline stages; programmable tiles; tiled architecture processor; two-dimensional mesh; Computer architecture; Delay; Energy consumption; Energy management; Frequency; Microprocessors; Network-on-a-chip; Pipelines; Silicon; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231942

Filename

1231942