System synthesis using behavioural descriptions

The authors present an architectural synthesis system. The system is able to generate multiprocessor architectures from behavioural descriptions. It combines the flexibility of so called high level synthesis systems with the higher throughput rates of DSP synthesis systems. After a short introduction into the CADDY system the impacts of mutual exclusion are briefly discussed. Then a new scheduling algorithm based on delay prediction and a new allocation algorithm based on a graph colouring approach are presented, that take data dependencies in the register assignment into account