Multiple voltage and frequency scheduling for power minimization

This paper presents a resource-constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages and varied clock frequency. The resource constrained scheduling is achieved by performing a constructive, force-directed scheduling. The proposed algorithm consists of two phases, the voltage assignment phase and the clock frequency variation phase. It also includes a pre processing phase of node minimization, where redundant nodes are eliminated. In the first phase the assignment of voltages to each functional unit is performed based on its occurrence on the critical path. In the next stage, the clock frequency for each control step is varied by using the clock frequency of the maximum number of operation type in that control step. It is taken care that, the total execution delay does not exceed the timing constraint given by CP /spl les/ /spl alpha/ < 2CP, where ´/spl alpha/´ is a certain factor of the critical path time delay (CP). The power consumed in the level shifters is also taken into consideration. The power consumed is compared with the power consumed by operating all functional units at the maximum available voltage and maximum clock frequency. A power reduction of about 40-65% has been achieved.