Test generation for multiple stuck-open faults in CMOS logic circuits

Author

Wang, Jhing-Fa ; Kuo, Tah-Yuan ; Lee, Jau-Yien

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1989

fDate

25-28 Sep 1989

Lastpage

38139

Abstract

A test generation procedure to derive robust two-pattern tests for stuck-open faults is presented, based on the concept of using single-fault test sets for multiple-fault detection. If the tests of all single stuck-open faults at the checkpoints can be obtained, the resulting test set will detect all the multiple stuck-open faults in the circuit. It is shown how the fault selection ordering affects the fault coverage, and a fault selection rule is suggested to improve the test generation and fault coverage. A test generation system based on the test generation procedure and fault selection rule has been implemented in C language on a SUN workstation. Several examples are given to demonstrate the versatility of the test generation procedure

Keywords

C language; CMOS integrated circuits; automatic testing; fault location; integrated logic circuits; logic testing; C language; CMOS logic circuits; SUN workstation; fault selection ordering; fault selection rule; multiple stuck-open faults; robust two-pattern tests; single-fault test sets; test generation procedure; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Robustness; Sun; System testing; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123195

Filename

123195