A VLIW architecture for logarithmic arithmetic

The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally belong to the same class of one-cycle-latency instructions like integer addition, subtraction and shifting. LNS addition is harder, requiring several cycles if the integer add determines the clock. Unlike prior LNS Instruction Set Architectures (ISAs), the proposed ISA uses a separate pipelined unit specialized for LNS addition that operates in parallel to a faster LNS-multiply-divide/integer-add unit. Their latencies are different: the former uses four to six cycles; the latter uses only one. The proposed Very Long Instruction Word (VLIW) architecture includes novel LNS increment-multiply and input-conversion instructions that improve performance at very low cost. The ISA overloads a novel comparison flag: LNS-less-than for divide and integer-less-than for subtract. Features of other ISAs are omitted here due to hidden costs of feeding extra operands to the ALUs. The proposed ISA offers multiplication bandwidth equal to (not higher than) that of addition. Also, omitting a multiply-accumulate instruction does not degrade LNS performance at all.