DocumentCode
2078964
Title
Back-traced deductive-parallel fault simulation for digital systems
Author
Hahanov, Vladimir ; Ubar, Raimund ; Hyduke, Stanley
fYear
2003
fDate
1-6 Sept. 2003
Firstpage
370
Lastpage
377
Abstract
A high performance back-traced deductive-parallel (BDP) fault simulation method based on the superposition procedure is oriented on using large digital designs processing. Evaluation of RT and gate level design description is proposed in this work. The data structure and program are developed for algorithms realization of the proposed method and integration with automatic test pattern generation systems.
Keywords
automatic test pattern generation; digital signal processing chips; fault simulation; integrated circuits; automatic test pattern generation; back-traced deductive-parallel fault simulation; digital designs processing; digital systems; fault analysis model; parallel simulation; reconvergent fan-outs; Algorithm design and analysis; Analytical models; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Digital circuits; Digital systems; Process design; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, 2003. Proceedings. Euromicro Symposium on
Conference_Location
Belek-Antalya, Turkey
Print_ISBN
0-7695-2003-0
Type
conf
DOI
10.1109/DSD.2003.1231969
Filename
1231969
Link To Document