A GaAs 600 Mbit/s 24B1P coder/decoder ASIC

Author

Parrilla, Mark L. ; Skellern, David J. ; Mahon, Simon J. ; Percival, Terence M.

Author_Institution

Sch. of Electr. Eng., Sydney Univ., NSW, Australia

fYear

1989

fDate

25-28 Sep 1989

Lastpage

37987

Abstract

The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented

Keywords

III-V semiconductors; application specific integrated circuits; cellular arrays; codecs; integrated logic circuits; 1.3 Gbit/s; 24B1P coder/decoder ASIC; 600 Mbit/s; GaAs; asynchronous control circuitry; data accelerator/decelerator; economics; standard cells; Application specific integrated circuits; Australia; Communication industry; Decoding; Gallium arsenide; High speed optical techniques; Marine technology; Optical fiber communication; Optical fibers; Underwater vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123197

Filename

123197