Power/area analysis and optimization of a DS-SS receiver for an integrated sensor microsystem

Communication systems targeting miniaturized sensor microsystem networks are characterized by their restricted power and area constraints. When considering the design of telecommunication system for such a network, the receiver is the key performance critical block. This paper describes research work carried out on studying the impact of input data characteristics and resolution and internal data path complexity on area and power performance of the receiver. We have constructed a number of transmitter/receiver architectures and analyzed their power/area. We demonstrate that up to 59% and 11% savings in area and power respectively could be achieved by optimizing input data size and internal register width for a particular application while maintaining signal quality.