Distributing SoC simulations over a network of computers

Author

Riihimäki, Jouni ; Helminen, Väinö ; Kuusilinna, Kimmo ; Hämäläinen, Timo D.

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

fYear

2003

fDate

1-6 Sept. 2003

Firstpage

447

Lastpage

450

Abstract

This paper presents parallelization of System-on-Chip (SoC) simulation over a network of computers. A custom C-language-based SoC exploration and simulation tool, Discrete Time Network Simulator (DTNS), is used to examine the problem. Parallelization is implemented with either CORBA or TCP/IP sockets. The distributed DTNS architecture facilitates the analysis of computation requirements for reasonable distribution. The minimum execution time per distributed process for the parallelization to be profitable is 1.2ms with CORBA and 0.4ms with TCP/IP implementation. These results are based on our networked PCs running the Linux operating system. The same network is used to evaluate this distribution method in case of video encoder SoC simulation.

Keywords

circuit simulation; computer networks; digital simulation; distributed object management; system-on-chip; transport protocols; C-language-based SoC exploration tool; C-language-based SoC simulation tool; CORBA; TCP/IP sockets; computer networks; discrete time network simulator; distributed DTNS architecture; distributed simulation; parallel DTNS; system-on-chip simulation; Computational modeling; Computer architecture; Computer networks; Computer simulation; Concurrent computing; Disruption tolerant networking; Distributed computing; Sockets; System-on-a-chip; TCPIP;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design, 2003. Proceedings. Euromicro Symposium on

Conference_Location

Belek-Antalya, Turkey

Print_ISBN

0-7695-2003-0

Type

conf

DOI

10.1109/DSD.2003.1231981

Filename

1231981