Title :
Design model for minority-carrier well-type guard-rings in CMOS circuits
Author :
Chen, Ming-Jer ; Huang, Chih-Yao ; Tseng, Ping-Nan ; Tsai, Nun-Sian ; Wu, Ching-Yuan
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
A novel analytic model for minority-carrier well-type guard ring design has been developed for CMOS circuits. This model, expressed as a function of epi-layer thickness, well junction depth, and guard ring width, has been verified by two-dimensional numerical simulation as well as by experimental data. Also, the model has been confirmed to be valid by temperature measurements. The effect of a floating well-type guard ring has been addressed
Keywords :
CMOS integrated circuits; minority carriers; semiconductor device models; CMOS circuits; analytic model; epi-layer thickness; floating guard-ring; minority-carrier; two-dimensional numerical simulation; well junction depth; well-type guard-rings; Circuit simulation; Electron emission; Epitaxial layers; Numerical simulation; Poisson equations; Semiconductor device manufacture; Semiconductor device modeling; Substrates; Temperature measurement; Virtual manufacturing;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164068
