Digital logarithmic CMOS multiplier for very-high-speed signal processing

Author

Hoefflinger, B. ; Selzer, M. ; Warkowski, F.

Author_Institution

Inst. fuer Mikroelektronik Stuttgart, Germany

fYear

1991

fDate

12-15 May 1991

Abstract

Parallel digital logarithmic (DIGILOG) coding of n-bit data is implemented in CMOS with n/4 gate delays and a compression to (log₂n+m-1) bits for m -bit relative accuracy. Multiplication becomes an addition of logarithms with two parallel adders of length (1+log₂n ) and (m-1), respectively. Expansive decoding yields a 2 n-bit product. The transistor count of a DIGILOG multiplier can be less than one quarter and the multiplication time can be less than one half in comparison with a Booth-Wallace multiplier

Keywords

CMOS integrated circuits; digital arithmetic; digital signal processing chips; multiplying circuits; parallel architectures; Booth-Wallace multiplier; CMOS; DIGILOG multiplier; accuracy; addition of logarithms; compression; delays; digital logarithmic multipliers; expansive decoding; multiplication time; parallel adders; transistor count; very-high-speed signal processing; Adders; CMOS process; Decoding; Delay effects; Digital signal processing; Dynamic range; Encoding; Neural networks; Signal to noise ratio; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164069

Filename

164069