• DocumentCode
    2079727
  • Title

    Economic learning for thermal-aware power budgeting in many-core architectures

  • Author

    Ebi, Thomas ; Kramer, David ; Karl, Wolfgang ; Henkel, Jörg

  • fYear
    2011
  • fDate
    9-14 Oct. 2011
  • Firstpage
    189
  • Lastpage
    196
  • Abstract
    One of the key challenges for multi-core processors in the nano-CMOS era is dealing with the increased temperatures. It is imperative that peak temperatures are reduced and that heat is spread as evenly on the chip as possible to avoid mutual heating and high thermal gradients between processor cores. Approaches have emerged which share a global power budget among multiple cores in order to meet these objectives. However, while these approaches act proactively in distributing power across the chip before thermal problems arise, changes in the respective strategies remain reactive to a temperature threshold. Our approach uses reinforcement learning in order to dynamically change what we call power trading strategies before thermal thresholds are hit based on past recorded observations. Through learning, our hierarchical approach is also able to distribute so-called multiple power budgets at once thereby making power trading more effective, reaching a decrease in peak temperatures of around 4% compared to a fully distributed approach - which can be critical at near-threshold temperatures in terms of transient errors - while also decreasing the number of deadline misses by a factor of 7. Our technique has been verified by deploying a thermal camera.
  • Keywords
    CMOS integrated circuits; learning (artificial intelligence); multiprocessing systems; power aware computing; economic learning; many-core architecture; multicore processor; nanoCMOS era; power trading strategy; reinforcement learning; thermal camera; thermal threshold; thermal-aware power budgeting; Computer architecture; Economics; Heating; Monitoring; Power demand; Temperature measurement; Thermal management; Agent-Based Systems; Dynamic Thermal Management; MPSoCs; Multi-Core Architectures; Proactive Algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4503-0715-4
  • Type

    conf

  • Filename
    6062288