A bursty multi-port memory controller with quality-of-service guarantees

Embedded multimedia system-on-chips place an increasing demand on Multi-Port Memory Controllers (MPMCs) for higher memory system performance and energy efficiency, in addition to satisfying various types of quality-of-service requirements, such as minimum latency and bandwidth guarantees. While previous works have attempted to target different aspects of the MPMC design challenges, none has succeeded in addressing all these problems simultaneously. In this paper, we propose a new approach that can provide, not only minimum latency and bandwidth guarantees, but also higher efficiency in utilization of physical DRAM bandwidth and dynamic bandwidth made available by underutilized ports. Experimental results showthat, on typical multimedia workloads, our approach improves the effective DRAM bandwidth and energy efficiency by as much as 1.9× and 1.49×, respectively. In addition, the response latency for latency-sensitive port is improved by more than 10X, while preserving bandwidth guarantee for all ports.