Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems

Recent advances in silicon photonic device and fabrication technologies make silicon photonic interconnect a promising communication fabric to address the inter-core and inter-die interconnect challenges for future embedded many-core processors. Informed design decisions in silicon photonic interconnection require optimization of performance, power efficiency, and reliability for different application scenarios. Optimizing these network and system metrics require understanding of silicon photonics device characteristics. However, existing design space exploration methodologies rely on time-consuming electromagnetic simulations or measurement of fabricated devices. In this paper, we introduce analytical models of devices, explore their design spaces, and apply them to different applications. The analytical models consist of parametrized transfer-matrices, with parameters categorized as fabrication-induced parameters and design parameters. Fabrication-induced parameters can be calibrated against measurements of fabricated devices to achieve high accuracy, whereas design parameters help in extrapolating the device characteristics. We develop and calibrate analytical models of widely used passive and doped micro-ring resonators. Three case studies of silicon photonic interconnects are discussed to represent different embedded applications and quantify the design trade-offs including performance requirements, power efficiency, and reliability constraints from the network system level.