DocumentCode :
2079968
Title :
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Author :
Huang, Jia ; Blech, Jan Olaf ; Raabe, Andreas ; Buckl, Christian ; Knoll, Alois
Author_Institution :
Fortiss GmbH, Munich, Germany
fYear :
2011
fDate :
9-14 Oct. 2011
Firstpage :
247
Lastpage :
256
Abstract :
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are often utilized. In this paper, we tackle the problem of analysis and optimization of fault-tolerant task scheduling for multiprocessor embedded systems. A set of existing fault-and process-models are adopted and a Binary Tree Analysis (BTA) is proposed to compute the system-level reliability in the presence of software/hardware redundancy. The BTA is integrated into a multi-objective evolutionary algorithm via a two-step encoding to perform reliability-aware design optimization. The optimization results contain the mapping of tasks to processing elements, the exact task and message schedule and the fault-tolerance policy assignment. Based on the observation that permanent faults need to be considered together with transient faults to achieve optimal system design, we propose a virtual mapping technique to take both types of faults into account. To the best of our knowledge, this is the first approach in fault-tolerant task scheduling that considers permanent and transient faults in a unified manner. The effectiveness of our approach is illustrated using several case studies.
Keywords :
embedded systems; fault tolerance; multiprocessing systems; processor scheduling; binary tree analysis; fault-tolerance policy assignment; fault-tolerant task scheduling; hardware replication; multiobjective evolutionary algorithm; multiprocessor embedded system; reliability-aware design optimization; safety-related system; software reexecution; software/hardware redundancy; system-level reliability; two-step encoding; virtual mapping; Complexity theory; Fault tolerant systems; Redundancy; Schedules; Transient analysis; Design Optimization; Embedded Systems; Reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4503-0715-4
Type :
conf
Filename :
6062296
Link To Document :
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