Exploiting temporal decoupling to accelerate trace-driven NoC emulation

The need for hardware acceleration of Network-on-Chip (NoC) simulation has been motivated by their growing complexity and large design space. NoC simulation can exploit the inherent concurrency in hardware by using FPGA based emulators. For trace-driven NoC emulators, we enhance this raw hardware speedup by exploiting the traffic characteristics for a more efficient utilization of hardware. We propose a technique, OTO-NoC-Sim, to reduce NoC emulation time by scheduling network transactions in an out-of-time order. Our simulation technique addresses the challenges arising out of an out-of-time-order scheduling in maintaining the correctness of statistics measured. Our experiments indicate that our proposed technique reduces the average emulation time by 3× for multi-threaded applications and by 3.5× for multi-programmed benchmarks when compared to a conventional FPGA emulation.