Title :
A data-flow processor for real-time low-level image processing
Author :
Quénot, Georges ; Zavidovique, B.
Author_Institution :
Lab. Syst. de Perception, DGA/Etablissement Tech., Central de l´´Armement, Arcueil, France
Abstract :
A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 Mbyte/s data flows and performs up to 50 million 8- or 16-b arithmetic operations per second. The chip has been processed in a 1-μm CMOS technology. It includes 160000 transistors in a 84 mm2 die size area; its clock is at 25 MHz; and it is packaged in a 144-pin PGA package. The approach is to perform computations on the fly on a data flow that comes from a digital video camera. The set of available operators on the DFP has been defined to cover as widely as possible the range of low-level image processing functions
Keywords :
CMOS integrated circuits; computerised picture processing; digital signal processing chips; parallel architectures; 1 micron; 25 Mbyte/s; CMOS technology; PGA package; arithmetic operations; data-flow processor; die size area; digital video camera; low-level image processing functions; real-time low-level image processing; Arithmetic; CMOS process; Circuits; Clocks; Computer architecture; Digital cameras; Dissolved gas analysis; Electronics packaging; Image processing; Physics computing;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164071
