Optimizing addition for sub-threshold logic

Digital circuits operating at subthreshold-voltage levels can achieve extremely low energy consumption. Typical applications include sensor processors with modest processing requirements that must run for long intervals on a low energy supply. The design goal is to minimise the total energy required for a processing task. Optimal architectures strike a balance between leakage and dynamic dissipation: if a unit is too slow, leakage energy is wasted throughout the system; however increasing the unit´s speed may cost increased dynamic dissipation and leakage within the unit. We examine this trade-off through the simulation of a variety of adder architectures. The results show that for a 180 nm process, system leakage dominates adder switching energy. For all but the smallest systems, when the adder is on the critical timing path, overall energy consumption is minimized by choosing a fast tree adder. The results also show that high valency tree adders perform well at subthreshold levels in this process.