A 32 Mb/s disk drive data separator for constant density recording

The authors describe a data separator LSI that has been developed for use in hard disk drives for constant density recording. The data separator LSI has a built-in read clock pulse recovery PLL (phase-locked loop) and write clock pulse generator PLL that can divide and program transfer rates with double frequency range into 32 steps. The COV has a clock pulse jitter of 0.4 ns and functions for switching center frequencies so that it can handle all transfer rates. The read clock pulse recovery PLL, required for especially critical programming of constants, divides programmable transfer rates into two groups, one for low speeds and the other for high speeds, and it has functions for independent programming of natural frequency and damping factor. Use of the 2-μm BiCMOS process allows data coding and decoding at a maximum speed of 32 Mb/s and a power consumption of 440 mW