Title :
System-level design space exploration for three-dimensional (3D) SoCs
Author :
Zou, Qiaosha ; Chen, Yibo ; Xie, Yuan ; Su, Alan
Author_Institution :
Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield.
Keywords :
hardware-software codesign; integrated circuit interconnections; system-on-chip; three-dimensional integrated circuits; 3D SoC integration; 3DIC; hardware/software co-synthesis; integration density; interconnect scaling; optimal design; system-level design space exploration; system-on-chip; three-dimensional SoC; Computer architecture; Hardware; Microprocessors; Resource management; Software; System-on-a-chip; Three dimensional displays;
Conference_Titel :
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4503-0715-4