System Level Analysis of Interference Aware LMMSE Chip Equalization in HSDPA Network

In this paper we present a system level performance analysis of ideally interference aware linear minimum mean squared error (LMMSE) chip-level equalizer capable of both intra-cell and inter-cell interference suppression with high-speed downlink packet access (HSDPA). The evaluation is performed with and without receive diversity, having the intra-cell interference suppressing LMMSE equalizer as a reference. The study is performed with fully dynamic system simulator which includes the modeling of LMMSE equalizer, HSDPA functionality, UE mobility and the most fundamental radio resource management algorithms. The used system scenario is HSDPA network with proportional fair scheduler. The results indicate that having ideal knowledge of interference in LMMSE equalizer would provide benefits for the end user by increasing the achievable data rates at the cell edges but having a minor effect to the average system performance.