Dynamic asynchronous logic for high speed cMOS systems

It is pointed out that as chip switching speed improves, asynchronous logic becomes potentially faster than synchronous logic if it exploits the benefits of dynamic logic. The author describes a chip with dynamic asynchronous logic, running at 500 MHz in 2-μm CMOS. He proposes using acknowledged asynchronous logic for local communication, where the acknowledgment delay is small, while using asynchronous FIFOs (first in, first outs) for phase alignment of long distance communication, such as chip-to-chip signaling. To guarantee refresh, independent of the data, he proposes exploiting the phase changes in four-state logic