Title :
Dynamic asynchronous logic for high speed cMOS systems
Author :
McAuley, Anthony J.
Author_Institution :
Bellcore, Morristown, NJ, USA
Abstract :
It is pointed out that as chip switching speed improves, asynchronous logic becomes potentially faster than synchronous logic if it exploits the benefits of dynamic logic. The author describes a chip with dynamic asynchronous logic, running at 500 MHz in 2-μm CMOS. He proposes using acknowledged asynchronous logic for local communication, where the acknowledgment delay is small, while using asynchronous FIFOs (first in, first outs) for phase alignment of long distance communication, such as chip-to-chip signaling. To guarantee refresh, independent of the data, he proposes exploiting the phase changes in four-state logic
Keywords :
CMOS integrated circuits; asynchronous sequential logic; integrated logic circuits; many-valued logics; 2 micron; 500 MHz; acknowledgment delay; asynchronous FIFOs; chip-to-chip signaling; dynamic asynchronous logic; four-state logic; high speed cMOS systems; local communication; long distance communication; phase alignment; Application specific integrated circuits; CMOS logic circuits; Clocks; Communication switching; Equations; Frequency; Hazards; Latches; Pipelines; Propagation delay;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164074
