Title :
A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency
Author :
Apostolidou, M. ; van der Heijden, M.P. ; Leenaerts, D.M.W. ; Sonsky, J. ; Heringa, A. ; Volokhine, I.
Author_Institution :
NXP Semicond. Res., Eindhoven
fDate :
June 17 2008-April 17 2008
Abstract :
A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF power amplifiers; CMOS technology; Class E RF power amplifier; cascode stage; frequency 2 GHz; power added efficiency; power-added efficiency; self-biasing; size 65 nm; Breakdown voltage; CMOS process; CMOS technology; Character generation; MOSFETs; Power amplifiers; Power generation; Radio frequency; Radiofrequency amplifiers; Topology; CMOS PA; HV device; PAE; cascode; class-E; driver stage; self-biasing technique;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-1808-4
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2008.4561404
