Title :
Some relationships between delay testing and stuck-open testing in CMOS circuits
Author :
David, R. ; Rahal, S. ; Rainard, J.-L.
Author_Institution :
Lab. d´´Automatique, ENSIEG/INPG, CNRS, Grenoble, France
Abstract :
Various kinds of faults must be tested in CMOS circuits. Testing of an excessive delay as well as testing of a stuck-open fault requires a sequence of two successive input vectors. It has been observed by many authors that there are some similarities between delay testing and stuck-open testing. In this paper it is shown that if all the delay faults have been robustly tested in a combinational circuit, then all the stuck-open faults have been robustly tested too
Keywords :
CMOS integrated circuits; combinatorial circuits; delays; fault location; integrated circuit testing; CMOS circuits; combinational circuit; delay testing; stuck-open fault; stuck-open testing; successive input vectors; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Fault detection; Logic circuits; Propagation delay; Robustness; Semiconductor device modeling; Variable structure systems;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136670
