Keywords :
circuit CAD; circuit layout CAD; formal verification; integrated logic circuits; logic CAD; optimisation; ATPG; BDD; Boolean methods; collaborative design; deep submicron digital designs; design optimisation; design reuse; embedded system design; formal verification; functional simulation; functional verification; high level synthesis; interconnect modelling; logic optimisation; logic testing; mixed-signal design; partitioning; performance modelling; placement; power optimization; processor design; programable logic; state space methods; timing analysis;
