Title :
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks
Author :
Darlay, F. ; Courtois, B.
Author_Institution :
IMAG/TIM3 Lab., Grenoble, France
Abstract :
This paper addresses the problem of generating robust tests (tests which are efficient even in the presence of arbitrary delays) for stuck-open faults, in CMOS logic networks. The authors´ approach consists of a topological analysis leading to the definition of a criterion which allows them to distinguish between robustly and non-robustly testable gates. They also present a new design for testability method, to be applied to non-robustly testable gates
Keywords :
CMOS integrated circuits; fault location; integrated logic circuits; logic testing; design for testability; reconvergent fan-out CMOS logic networks; robust tests; stuck-open faults; topological analysis; CMOS logic circuits; Circuit faults; Circuit testing; Design for testability; Fault detection; Hazards; Laboratories; Logic design; Logic testing; Robustness;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136671
