Performance debugging of parallel and distributed embedded systems

Validation, a crucial stage in the development cycle of embedded systems, is normally carried out using static analysis based on scheduling techniques. In high performance embedded systems, where several tasks with high computing requirements are working on input and output signals with high sampling rates, parallel and distributed processing is a valuable design alternative in order for the system to achieve the fulfillment of its real-time constraints. When the validation of parallel and distributed embedded systems is considered, many simplifications are made in order to make analysis tractable. This means that even if the system can be statically validated, the real behaviour of the system in execution may be different enough from its theoretical behaviour to make it invalid. Thus, conservative designs that lead to over-dimensioned systems with partially wasted resources are commonly adopted. Although static analysis is the only alternative in case of critical embedded systems, where the fulfillment must be always guaranteed, dynamic analysis, based on measurement, is an interesting alternative for validation of non-critical embedded systems. This paper describes a methodology for performance debugging of parallel and distributed embedded systems with non-critical end-to-end deadlines. The methodology is based on the measurement of a prototype of the system in execution and is supported by a behavioural model