Innovative process architectures for rapid cycle-time sub 0.5 μm CMOS

New semiconductor manufacturing equipment capability is providing significant process cycle-time advantages in three distinct ways. Clustering operations reduces the number of visits each wafer makes through a particular tool, with savings in wafer cleaning and loading stages. New process techniques, such as high pressure oxidation and RTP, can also provide dramatic reductions in process time. New equipment capability enables innovation in process architecture, to reduce the number of process steps. This paper focuses on means of reducing thermal process stages in sub 0.5 μm CMOS technology