Title :
A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link
Author :
Fukuda, Koji ; Ono, Goichi ; Watanabe, Keiki ; Muto, Takashi ; Yamashita, Hiroki ; Masuda, Noboru ; Nemoto, Ryo ; Suzuki, Eiichi ; Takemoto, Takashi ; Yuki, Fumio ; Yagyu, Masayoshi ; Toyoda, Hidehiro ; Kono, Masashi ; Kambe, Akihiro ; Umai, Seiichi ; Sai
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
Abstract :
The world\´s first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).
Keywords :
CMOS integrated circuits; Ge-Si alloys; demultiplexing equipment; integrated circuit design; large scale integration; local area networks; low-power electronics; multiplexing equipment; 100-Gigabit Ethernet link; 10:4 MUX Gearbox IC; 4:10 DEMUX Gearbox IC; CMOS; LSI; SiGe; bit rate 12.5 Gbit/s; bit rate 25 Gbit/s; large scale integration; low-power MUX; power 0.98 mW; power 14 mW; power 2 W; size 65 nm; Clocks; Large scale integration; Optical receivers; Phase locked loops; Power demand; Voltage-controlled oscillators;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2011 IEEE
Conference_Location :
Waikoloa, HI
Print_ISBN :
978-1-61284-711-5
Electronic_ISBN :
1550-8781
DOI :
10.1109/CSICS.2011.6062438
