Standard Verilog-VHDL interoperability

During the last few years HDLs have become the driver behind the move to top down design in the electronic design industry. Two HDLs, VHDL and Verilog HDL have become the dominant de facto industry standard HDLs. Since the industry has made a huge investment in both HDLs and there is every indication that each will retain significant market share for the foreseeable future, it is critical that there exist a standard methodology for interoperability between the two languages. This paper describes the relevant issues for interoperability and suggests solutions where they currently exist. It further summarizes the work which needs to be done for a complete solution and the groups who are involved in achieving this goal. The emphasis in this paper is on simulation since the semantics of the two languages are specified only for that discipline. While the importance of other disciplines such as logic synthesis cannot be underestimated in the top down design process, the lack of standard language semantics makes general analysis problematic