Experiences in testing and debugging the i960 MX VHDL model

We describe design decisions made while testing and debugging our behavioral VHDL model of the Intel i960 MX processor. The model provides human readable representations of processor information, to simplify debugging and documentation. An interactive simulation, using an X window interface, aids in debugging the VHDL model and application software. We developed an automated result checking entity to verify instruction operation tests and a flexible method to generate Chebyshev approximations of transcendental functions and check their results