DocumentCode :
2081771
Title :
A data-structuring technique for gridded VLSI layouts
Author :
Haider, Saleem M. ; Ang, Peng H.
Author_Institution :
Syst. Res. Lab, LSI Logic Corp., Menlo Park, CA, USA
fYear :
1990
fDate :
12-15 Mar 1990
Firstpage :
356
Lastpage :
362
Abstract :
This paper presents the linked array data structure for storing rectangular structures which are constrained to a grid. The data structure is particularly useful in integrated layout systems for VLSI technologies like gate-arrays; it is also useful for building schematic editors. This data structure has been used to implement a prototype layout system which has significant memory usage and timing response advantages for large layouts (~100000 used gates, running on a workstation like SUN 3/260). The paper describes how the data structure is created, how it operates, and how it compares with existing mechanisms
Keywords :
VLSI; circuit layout CAD; data structures; logic arrays; data-structuring technique; gridded VLSI layouts; integrated layout systems; linked array; memory usage; schematic editors; timing response; Buildings; Data structures; Large scale integration; Logic arrays; Routing; Strips; Tiles; Timing; Very large scale integration; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
Type :
conf
DOI :
10.1109/EDAC.1990.136673
Filename :
136673
Link To Document :
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