DocumentCode :
2081826
Title :
VMS: a VHDL Modeling System
Author :
Lakshmikantam, Ch. ; Manohar, S.
Author_Institution :
Texas Instrum. (India), Bangalore, India
fYear :
1994
fDate :
1-4 May 1994
Firstpage :
58
Lastpage :
65
Abstract :
VMS (VHDL Modeling System) is a tool which automates the model generation of ASIC gate level cells for VHDL logic simulators. VMS is a rule-based system and has built into it the expertise of model developers in the form of rules. VMS handles many of the complex and intricate model behaviors, and is a high productivity tool
Keywords :
application specific integrated circuits; circuit analysis computing; intelligent design assistants; logic CAD; specification languages; ASIC gate level cells; VHDL Modeling System; VHDL logic simulators; VMS; automatic model generation; complex model behaviors; high productivity tool; rule-based system; Application specific integrated circuits; Design methodology; Equations; Logic design; Object oriented databases; Object oriented modeling; Productivity; Software libraries; Timing; Voice mail;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VHDL International Users Forum. Spring Conference, 1994. Proceedings of
Conference_Location :
Oakland, CA
Print_ISBN :
0-8186-6215-8
Type :
conf
DOI :
10.1109/VIUF.1994.323965
Filename :
323965
Link To Document :
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