Hierarchical partitioning of high-level VHDL structures

A systematic hierarchical partitioning algorithm for high-level VHDL descriptions is proposed. The partitioning algorithm is based on quadrisection. The major contributions of this paper include exploiting the VHDL hierarchy for the local expansion of VHDL entities and the extension of regular quadrisection to a three-stage hierarchical operation. At each hierarchical level, the complexity of our algorithm is linear in the number of nets. The results show that our hierarchical algorithm provides solutions which are better than the min-cut algorithm and compatible with flat quadrisection