Title :
A mathematical level/strength model for synthesizing STD-LOGIC-1164 values
Author :
Vellenga, James H.
Author_Institution :
Viewlogic Systems Inc., Marlboro, MA, USA
Abstract :
STD-LOGIC-1164 values let a VHDL user represent known and unknown signal values based on two levels (0 and 1) and three strengths. This paper formalizes a two-part level/strength model for STD-LOGIC-1164 values to develop strength-related transformations that can be used in synthesis. We represent unknowns as a set of choices among possible well-defined (“real”) values. This lets us formally define “implementation” as the process of narrowing the set of choices. Defining “strong equivalence” (levels and strengths) and “weak equivalence” (levels only) then allows one to determine, for example, under what conditions “OR/AND” logic can be considered (logically) equivalent to a bus with weak and high-impedance drivers. The formalism is used to study the composition of resolution functions, and to compare them to equivalent hardware implementations
Keywords :
logic CAD; specification languages; OR/AND logic; STD-LOGIC-1164 value synthesis; VHDL; bus; equivalent hardware implementations; high-impedance drivers; logic simulation; mathematical level/strength model; resolution functions; strength-related transformations; strong equivalence; weak drivers; weak equivalence; Control system synthesis; Hardware; Impedance; Libraries; Logic; Mathematical model; Multiplexing; Signal design; Signal resolution; Signal synthesis;
Conference_Titel :
VHDL International Users Forum. Spring Conference, 1994. Proceedings of
Conference_Location :
Oakland, CA
Print_ISBN :
0-8186-6215-8
DOI :
10.1109/VIUF.1994.323968
