A 40GHz fractional-n frequency synthesizer in 0.13μm CMOS

Author

Hung, Chao-Ching ; Shen, Ding-Shiuan ; Liu, Shen-Iuan

Author_Institution

Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2008

fDate

June 17 2008-April 17 2008

Firstpage

295

Lastpage

298

Abstract

A 40 GHz fractional-N frequency synthesizer with a divide-by-64/64.5/65/65.5 fractional multi-modulus divider (MMD) is presented. A second-order 24-bit delta-sigma modulator is used to modulate the fractional MMD. This fractional MMD provides a half division step of a conventional integer MMD. Therefore, a better frequency resolution can be obtained. This frequency synthesizer has been fabricated in a 0.13 um CMOS process. The measured fractional spur is below -50dB. The measured phase noise is -75.3 dBc/Hz and -93.24 dBc/Hz at 1MHz and 3 MHz offset, respectively. The die area is 1.34 x 1.26 mm² and the power dissipation is 105 mW from the supply of 1.5 V.

Keywords

CMOS integrated circuits; MIMIC; delta-sigma modulation; frequency dividers; frequency synthesizers; CMOS; delta-sigma modulator; fractional multimodulus divider; fractional-N frequency synthesizer; frequency 40 GHz; measured phase noise; power 105 mW; size 0.13 mum; voltage 1.5 V; Circuits; Degradation; Delta modulation; Frequency conversion; Frequency synthesizers; Phase frequency detector; Phase noise; Power dissipation; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE

Conference_Location

Atlanta, GA

ISSN

1529-2517

Print_ISBN

978-1-4244-1808-4

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2008.4561439

Filename

4561439