A VHDL based test environment including models for equivalence fault collapsing

In the area of digital systems testing, fault collapsing is the process of reducing the faults in a circuit to only those that can be distinguished. In local fault collapsing, one fault is selected from each of the equivalent fault classes of the logic gates. The selection is based on the connections made to the ports of a gate. We have developed VHDL gate models for local equivalent fault collapsing. This paper presents a VHDL based test environment that uses fault collapsing VHDL models to generate a list of faults for test generation and fault simulation. Our VHDL modeling strategy and some examples are discussed