Title :
UASSNS 3.1: an integrated design and analysis tool for SSO noise in leadframe packages
Author :
Huang, Chender ; Lin, Lei ; Prince, John L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
This paper introduces an integrated design and analysis CAD tool for SSO noise in PQFP leadframe packages. The CAD tool incorporates very efficient design and analysis algorithms which enable an accurate estimate of the maximum Simultaneous Switching Output Noise and the required numbers and placement of power and/or ground pins for pre-specified SSO noise limits in the initial design stage. Pre-specified package SSO noise is analyzed by using fast effective inductance reduction technique and SPICE simulation or analytic formulae
Keywords :
CAD; integrated circuit design; integrated circuit noise; integrated circuit packaging; plastic packaging; CAD tool; PQFP leadframe package; SPICE simulation; UASSNS 3.1; analysis algorithm; design algorithm; inductance; simultaneous switching output noise; Algorithm design and analysis; Cause effect analysis; Circuit noise; Design automation; Electronics packaging; Inductance; Product design; Semiconductor device noise; Semiconductor device packaging; Signal design;
Conference_Titel :
Electronic Components and Technology Conference, 1997. Proceedings., 47th
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-3857-X
DOI :
10.1109/ECTC.1997.606247
