Title :
Realization of Logic Operations Through Optimized Ballistic Deflection Transistors
Author :
Kaushal, V. ; Margala, M. ; Iñiguez-de-la-Torre, I. ; González, T. ; Mateos, J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Lowell, MA, USA
Abstract :
In this paper, the utilization of recently proposed ballistic deflection transistors (BDT) is investigated for the realization of the complete family of logic functions. BDT performance is optimized through its structural modification which is followed by the Monte Carlo simulations for 2- input logic gate functionalities at room temperature. BDT is a quasi-ballistic planar device based on InGaAs/InAlAs/InP heterolayer. The faster non-scattering transport obtained in the two dimensional electron gas (2DEG) layer facilitates smaller transit time and high performance needed for high speed circuitry.
Keywords :
Monte Carlo methods; logic gates; transistors; two-dimensional electron gas; 2-input logic gate functionalities; Monte Carlo simulations; logic operations; optimized ballistic deflection transistors; quasiballistic planar device; two dimensional electron gas layer; Logic functions; Logic gates; Monte Carlo methods; Multiplexing; Nanoscale devices; Performance evaluation; Transistors;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2011 IEEE
Conference_Location :
Waikoloa, HI
Print_ISBN :
978-1-61284-711-5
Electronic_ISBN :
1550-8781
DOI :
10.1109/CSICS.2011.6062471
