A design representation for high level synthesis

TAO is a hierarchical graph representation of behaviour for high level synthesis of hardware structures. Typically a high level synthesis system takes a behavioural description and a set of constraints as input and generates a structural description of a hardware realization as output. One of the main questions when realizing an internal design representation is what data structures should be used to reduced time complexity of algorithms applied and how to organize these data structures. When using the TAO graph representation one must consider several types of graphs operations such as node merge and distribution. These require different representations to reduce the overall computational complexity of the procedure at hand. In this paper data structures for the three levels of TAO, task, algorithm, and operation graphs, are selected, defined, and discussed with examples of typical graph operations performed during the synthesis process from a behavioural towards a structural description