When are transmission-line effects important for on-chip interconnections

Author

Deutsch, A. ; Kopcsay, G.V. ; Restle, P. ; Katopis, G. ; Becker, W.D. ; Smith, H. ; Coteus, P.W. ; Surovic, C.W. ; Rubin, B.J. ; Dunne, R.P. ; Gallo, T. ; Jenkins, K.A. ; Terman, L.M. ; Dennard, R.H. ; Sai-Halasz, G.A. ; Knebel, D.R.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1997

fDate

18-21 May 1997

Firstpage

704

Lastpage

712

Abstract

Short, medium and long on-chip interconnections having line widths of 0.45-52 μm are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction

Keywords

crosstalk; delays; integrated circuit interconnections; transmission line theory; 0.45 to 0.52 micron; capacitive coupling; crosstalk; delay; design; five-metal-layer structure; global wiring; inductance; inductive coupling; local wiring; on-chip interconnection; power bus; resistance; resistive loss; transmission-line effects; Capacitance; Couplings; Crosstalk; Delay effects; Guidelines; Inductance; Integrated circuit interconnections; Space technology; Transmission lines; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1997. Proceedings., 47th

Conference_Location

San Jose, CA

ISSN

0569-5503

Print_ISBN

0-7803-3857-X

Type

conf

DOI

10.1109/ECTC.1997.606248

Filename

606248