Hierarchical layout verification for submicron designs

The author presents the program HEXDRC for hierarchical circuit extraction and design rule check. The main problem for hierarchical layout verification is to handle interactions between different cells effectively. The kind of interactions however strongly depends on the actual design style, so that it will be impossible to find a solution which will work optimal for all layouts. To solve this problem, HEXDRC offers a lot of possibilities to modify the implemented basic algorithm by user instructions. HEXDRC includes design rule checking and netlist extraction, both working on the same database. This allows to verify more complex rules than with separate tools. The author discusses the basic concept, describes how to adapt the program to a special design style and presents first experimental results