Title :
Simulation based verification of register-transfer level behavioral synthesis tools
Author :
Ernst, R. ; Sutarwala, S. ; Jou, J.-Y. ; Tong, M.
Author_Institution :
Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
Abstract :
The authors present a simulation based system for verification of register-transfer level behavioral synthesis tools. Applications are tool debugging and automatic regression test. Key feature is a transformation of sequential circuits for application of pseudo-random test patterns. The results show a high relevance of verification with pseudo-random patterns
Keywords :
circuit analysis computing; logic testing; automatic regression test; pseudo-random test patterns; register-transfer level behavioral synthesis tools; sequential circuits; simulation based verification; tool debugging; Automatic testing; Circuit simulation; Circuit synthesis; Circuit testing; Debugging; Formal verification; Hardware; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136680
