Title :
Fault grading operational self-test
Author :
Aparicio, Robert T. ; Hallinan, Patrick J.
Author_Institution :
G.M. Hughes Electron., Goleta, CA, USA
Abstract :
A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today´s CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed
Keywords :
automatic testing; computer testing; fault location; logic testing; Delco VHSIC 1750A computer; design guidelines; fault grading; fault simulation methodology; hardware accelerator; logic testing techniques; operational self-test; Built-in self-test; Circuit faults; Circuit simulation; Embedded computing; Hardware; Iron; Logic; Switches; Testing; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123221
