• DocumentCode
    2083641
  • Title

    Fault grading, a measure of logic simulation integrity

  • Author

    Greggain, Lance ; White, Bill

  • Author_Institution
    Genesis Microchip Inc., Markham, Ont., Canada
  • fYear
    1989
  • fDate
    25-28 Sep 1989
  • Lastpage
    38018
  • Abstract
    It is argued that although fault grading is generally used as a measure of the completeness of the test program, it has an even greater potential in measuring the integrity of the functional analysis as performed by the logic simulation. A brief description of stuck-at-1 and stuck-at-0 fault simulation is given. Fault simulation is contrasted with the typical controllability and observability measures, and the benefits of high fault coverage are examined. A number of standard techniques for improving fault coverage are discussed
  • Keywords
    circuit analysis computing; controllability; fault location; integrated circuit testing; logic CAD; logic testing; observability; ASIC development process; controllability; fault coverage; fault grading; functional analysis; logic simulation integrity; observability; stuck-at-0 fault simulation; stuck-at-1 fault simulation; Analytical models; Application specific integrated circuits; Circuit faults; Circuit simulation; Circuit testing; Costs; Functional analysis; Logic design; Logic testing; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
  • Conference_Location
    Rochester, NY
  • Type

    conf

  • DOI
    10.1109/ASIC.1989.123222
  • Filename
    123222